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1 of 14 features ? converts cmos sram into nonvolatile memory ? unconditionally write - protects sram when v cc is out of tolerance ? automatically switches to battery backup when v cc power failure occurs ? flexible memory organization - mode 0: 4 banks with 1 sra m each - mode 1: 2 banks with 2 srams each - mode 2: 1 bank with 4 srams each ? monitors voltage of a lithium cell and provides advanced warning of impending battery failure ? signals low - battery condition on active low battery warning output signal ? resets pro cessor when power failure occurs and holds processor in reset during system power - up ? 10% power - fail detection ? industrial temperature range of - 40c to +85c pin description v cci - +3.3v power supply input v cco - sram power supply output v bat - backup b attery input a, b - address inputs cei1 - cei4 - chip enable inputs ceo1 - ceo4 - chip enable outputs bw - battery warning output (open drain) rst - reset output (open drain) mode - mode input gnd - ground nc - no connection pin assignment ds1323 3.3v flexible nonvolatile controller with li thium battery monitor 19 - 5920; rev 5/12 1 2 3 4 20 19 18 17 5 6 7 8 9 10 11 12 13 14 15 16 nc ds1323e 20 - pin tssop (173 mil s ) v cci rst bw ceo1 ceo2 nc ceo3 ceo4 nc mode v cco v bat nc cei1 cei2 nc a/cei3 b/cei4 gnd
ds1323 2 of 14 description the ds1323 flexible nonvolatile controller with lithium battery monitor is a cmos circuit that solves the ap plication problem of converting cmos srams into nonvolatile memory. incoming power is monitored for an out - of - tolerance condition. when such a condition is detected, chip - enable outputs are inhibited to accomplish write protection and the battery is switch ed on to supply the srams with uninterrupted power. special circuitry uses a low - leakage cmos process which affords precise voltage detection at extremely low battery consumption. one ds1323 can support as many as four srams arranged in any of three memory configurations. in addition to battery - backup support, the ds1323 performs the important function of monitoring the remaining capacity of the lithium battery and providing a warning before the battery reaches end - of - life. because the open - circuit voltage of a lithium backup battery remains relatively constant over the majority of its life, accurate battery monitoring requires loaded - battery voltage measurement. the ds1323 performs such measurement by periodically comparing the voltage of the battery as it supports an internal resistive load with a carefully selected reference voltage. if the battery voltage falls below the reference voltage under such conditions, the battery will soon reach end - of - life. as a result, the battery warning pin is activated to signal the need for battery replacement. memory backup the ds1323 performs all the circuit functions required to provide battery - backup for as many as four srams. first, the device provides a switch to direct power from the battery or the system power su pply (v cci ). whenever v cci is less than the v cctp trip point and v cci is less than the battery voltage v bat , the battery is switched on to provide backup power to the sram. this switch has voltage drop of less than 0.2 volts. second, the ds1323 handles po wer failure detection and sram write - protection. v cci is constantly monitored, and when the supply goes out of tolerance, a precision comparator detects power failure and inhibits the four chip enable outputs in order to write - protect the srams. this is ac complished by holding ceo1 through ceo4 to within 0.2 volts of v cco when v cci is out of tolerance. if any cei is active (low) at the time that power failure is detected, the corresponding ceo signal is kept low until the cei signal is brought high again. once the cei signal is brought high, the ceo signal is taken high and held high until after v cci has returned to its n ominal voltage level. if the cei signal is not brought high by 1.5s after power failure is detected, the corresponding ceo is forced high at that time. this specific scheme for delaying write protection for up to 1. 5s guarantees that any memory access in progress when power failure occurs will complete properly. power failure detection occurs in the range of 2.8 to 3.0 volts.
ds1323 3 of 14 memory configurations the ds1323 can be configured via the mode pin for three different ar rangements of the four attached srams. the state of the mode pin is latched at v cci = v cctp on power - up. see figure 1 for details. memory configurations figure 1 mode = gnd (4 banks with 1 sram each): mode = v cco (2 banks with 2 sram each): mode = not connected (1 bank with 4 srams) : ds1323 ds1323 ds1323
ds1323 4 of 14 battery voltage monitoring the ds1323 automatically perf orms periodic battery voltage monitoring at a factory - programmed time interval of 24 hours. such monitoring begins within t rec after v cci rises above v cctp and is suspended when power failure occurs. after each 24 - hour period (t btcn ) has elapsed, the ds13 23 connects v bat to an internal 1m ? test resistor (r int ) for one second (t btpw ). during this one second, if v bat falls below the factory - programmed battery voltage trip point (v btp ), the battery warning output bw is asserted. while bw is active, ba ttery testing will be performed with period t btcw to detect battery removal and replacement. once asserted, bw remains active until the battery is physically removed and replaced by a fresh cell. the battery is still retested after each v cc power - up, however, even if bw was active on power - down. if the battery is found to be higher than v btp during such testing, bw is deasserted and regular 24 - hour testing resumes. bw has an open - drain output driver. battery replacement following bw activation is normally done with v cci nominal so that sram data is not lost. during battery replacement, the minimum time duration between old battery detachment and new bat tery attachment (t bdba ) must be met or bw will not deactivate following attachment of the new battery. should bw not deactivate for this reason, the new battery can be detached for t bdba and then re - attached to cle ar bw . note: the ds1323 cannot constantly monitor an attached battery because such monitoring would drastically reduce the life of the battery. as a result, the ds1323 only tests the battery for one second out of every 24 hours and do es not monitor the battery in any way between tests. if a good battery (one that has not been previously flagged with bw ) is removed between battery tests, the ds1323 may not immediately sense the removal and may not activate bw until the next scheduled battery test. if a battery is then reattached to the ds1323, the battery may not be tested until the next scheduled test. note: battery monitoring is only a useful technique when testing can be done regularly over t he entire life of a lithium battery. because the ds1323 only performs battery monitoring when v cc is nominal, systems which are powered down for excessively long periods can completely drain their lithium cells without receiving any advanced warning. to pr event such an occurrence, systems using the ds1323 battery monitoring feature should be powered up periodically (at least once every few months) in order to perform battery testing. furthermore, anytime bw is activated on the first bat tery test after a power - up, data integrity should be checked via checksum or other technique. power monitoring the ds1323 automatically detects out - of - tolerance power supply conditions and warns a processor - based system of impending power failure. when v c ci falls below the trip point level in the range of 3.0 to 2.8 volts (10% tolerance) (v cctp ), the v cci comparator activates the reset signal rst . rst also serves as a power - on reset during power - up. after v cci exc eeds v cctp , rst will be held active for 200ms nominal (t rpu ). this reset period is sufficiently long to prevent system operation during power - on transients and to allow t rec to expire. rst has an open - drain output dr iver. freshness seal mode when the battery is first attached to the ds1323 without v cc power applied, the device does not immediately provide battery - backup power on v cco . only after v cci exceeds v cctp will the ds1323 leave freshness seal mode. this mode allows a battery to be attached during manufacturing but not used until
ds1323 5 of 14 after the system has been activated for the first time. as a result, no battery energy is drained during storage and shipping. functional block diagram figure 2
ds1323 6 of 14 absolute maximum ratings voltage range on any pin relative to ground .......................................................................... - 0.3v to + 6.0v operating temperature range ................................................................................................... - 40 c to +85c storage temperature range .................................................................................................... - 55 c to +125c lead temperature (soldering, 10s ) ......................................................................................................... + 300c soldering temperature (reflow) ............................................................................................................. +260c this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. package thermal characteristics (note 1 ) tssop junction- to - ambient thermal resistance ( ja ) ................................................................................. 73.8 c/w junction- to - case thermal resistance ( jc ) .......................................................................................... 20 c/w note 1: package thermal resistances were obtained using the method described in jedec specification jesd51 - 7, using a four - layer board. for detailed information on package thermal considera tions, refer to www.maxim - ic.com/thermal - tutorial . recommended operating conditions (t a = - 40c to +85c . ) parameter symbol min typ max units notes supply voltage v cci 3.0 3.3 3.6 v 2 battery supply vol tage v bat 2.0 6.0 v logic 1 input v ih 2.0 v cci +0.3 v 3 logic 0 input v il - 0.3 0.6 v 3 dc electrical characteristics (v cci v cctp , t a = - 40c to +85c.) parameter symbol condition min typ max units notes supply current i cc1 ttl inputs 50 200 a 4 supply current i cc2 cmos inputs 30 100 a 4 , 5 ram supply voltage v cco v cci - 0.2 v ram supply current i cco1 v cco v cci - 0.2v 80 ma ram supply current i cco2 v cco v cci - 0.3v 140 ma v cc trip point v cctp 2.8 2.9 3.0 v v bat trip point v btp 2.5 2.6 2.7 v output current i oh 2.2v - 1 ma 6 , 7 output current i ol 0.4v 4 ma 6 , 7 input leakage i il - 1.0 +1.0 a output leakage i lo - 1.0 +1.0 a battery monitoring test load r int 0.8 1.2 1.5 m
ds1323 7 of 14 dc electrical characteristics (v cci < v bat ; v cci < v cctp , t a = - 40c to +85c. ) parameter symbol condition min typ max units notes battery current i bat 100 na 4 battery backup current i cco3 v cco v bat - 0.2v 500 a supply voltage v cco v bat - 0.2 v ceo output v ohl v bat - 0.2 v 8 capacitance (t a = +25c.) parameter symbol min typ max units notes input capacitance ( cei , mode) c in 7 pf output capacitance ( ceo , bw , rst ) c out 7 pf ac electrical characteristics (v cci v cctp , t a = - 40c to +85c.) parameter symbol min typ max units notes cei to ceo propagation delay t pd 15 25 ns ce pulse width t ce 1.5 s 9 v cc valid to end of write protection t rec 125 ms 10 v cc valid to cei inactive t pu 2 ms v cc valid to rst inactive t rpu 150 200 350 ms 7 v cc valid to bw valid t bpu 1 s 7 ac electrical characteristics (v cci < v cctp , t a = - 40c to +85c.) parameter symbol min typ max units notes v cc slew rate t f 150 s v cc fail detect to rst active t rpd 15 s 7 v cc slew rate t r 15 s ac electrical characteristics (v cci v cctp , t a = - 40c to +85c.) parameter symbol min typ max units notes battery test to bw active t bw 1 s 7 battery test cycle - normal t btcn 24 hr battery test cycle - warning t btcw 5 s battery test pulse width t btpw 1 s battery detach to battery attach t bdba 7 s battery attach to bw inactive t babw 1 s 7
ds1323 8 of 14 timing diagram: power -up note: if v bat > v cctp , v cco will begin to slew with v cci when v cci = v cctp .
ds1323 9 of 14 timin g diagram: power - down notes: if v bat > v cctp , v cco will slew down with v cci until v cci = v cctp .
ds1323 10 of 14 timing diagram: battery warning detection note: t bw is measured from the expiration of the internal timer to the activation of the battery warning outp ut bw . timing diagram: battery replacement
ds1323 11 of 14 notes: 2. all voltages referenced to ground. 3. in battery backup mode, inputs must never be below ground or above v cco . 4. measured with outputs open. 5. all inputs within 0.3v of ground or v cci . 6. me asured with a load as shown in figure 3. 7. bw and rst are open drain outputs and, as such, cannot source current. external pull - up resistors should be connected to these pins for proper operation. both bw and rst can sink 10ma. 8. chip enable outputs ceo1 ? ceo4 can only sustain leakage current in the battery backup mode. 9. t ce maximum must be met to ensure data integrity on power down. 10. ceo1 through ceo4 will be held high for a time equal to t rec after v cci crosses v cctp on power - up. 11. the ds1323 is recognized by underwriters laborator ies (ul) under file e99151. dc test conditions outputs open all voltages ar e referenced to ground ac test conditions output load: see below input pulse levels: 0 ? 3.0v timing measurement reference levels input: 1.5v output: 1.5v input pulse rise and fall times: 5ns output load figure 3 *including scope and jig capacitance
ds1323 12 of 14 typical operating characteristics (v cc = + 3.3v, t a = +25 c, unless otherwise specified . ) supply current ( a) supply current vs. temperature 30 35 40 45 50 55 -40 -20 0 20 40 60 80 temperature (c) v cc trip(v) v cc trip vs. temperature 2.5 2.55 2.6 2.65 2.7 2.75 2.8 2.85 2.9 2.95 3 -40 -20 0 20 40 60 80 temperature (c)
ds1323 13 of 14 typical operating characteristics (cont inued ) (v cc = + 3.3v, t a = +25 c, unless otherwise specified . ) ordering information part temp range operating voltage (v) package type ds1323+ - 40oc to +85oc 3.3 20 tssop ds1323+t&r - 40oc to +85oc 3.3 20 tssop + denotes a lead(pb) - free/rohs - compliant package. t&r = tape and reel. package information for the latest package outline in formation and land patterns, go to www.maxim - ic.com/packages . note that a ?+?, ?#?, or ? - ? in the package code indicates rohs status only. package drawings may show a different suffix character, but the draw ing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 20 tssop u20+1 21- 0066 90- 0116 /ce propagation delay vs. temperature 8 9 10 11 12 13 14 15 16 17 -40 -20 0 20 40 60 80 temperature (c) /ceo propagation delay, rising edge /ceo propagation delay, falling edge delay time (ns)
ds1323 14 of 14 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely emb odied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408 - 737 - 7600 ? 201 2 maxi m integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision date description pages changed 6/11 deleted references to 16 - pin dip and 16 - pin so packages; updated the absolute maximum ratings section; updated the recommended operating conditions , dc electrical characteristics , capacitance , ac electrical characteristics tables; updated notes ; updated the ordering information table; added the package information table 1, 3, 6, 7, 13 5/12 corrected absolute maximum ratings section for sa process; upd ated soldering information; added package thermal characteristics section 6, 7, 11

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